Z80 BASIC on a Cyclone IV FPGA

With a vague idea that FPGAs are cool and that I’d like to learn how to use them I picked up a cheap Cyclone IV development board and a knock-off Alter USB Blaster clone from AliExpress.

I didn’t really know what I was buying, this was simply the cheapest thing I could find. The spec is alright, 6272 logic elements and 256Kbits of RAM. The bit part is important – you’re going to construct your own RAM from IP blocks, and the bus could be any number of bits wide.

The programmer is exactly like the picture, it’s Altera branded but, you know, fake.

Inside it’s a PIC microcontroller and a 74LVC244A octal buffer. I guess it emulates an FTDI because when I configured OpenOCD to use it I use the FTDI driver.

VHDL

There’s two major languages for FPGA development, Verilog and VHDL. I’m not experienced enough to have an opinion on which is better, but the project that I extended was already written in VHDL, so that’s what I carried on with.

This is an Altera chip, so you need to use their Quartus software. Luckily, it’s available for Linux as well as Windows. It’s big, and you need to download an also-very-big board support package for the Cyclone IV after installing it, but that’s proprietary software for you.

I followed Grant Searle’s Multicomp instructions, updating them for the board that I have and the current version of Quartus.

Nothing I’ve done so far would have been possible without this excellent resource, you should read his whole site if you’re into retrocomputing or understanding how a microcomputer works.

I’ve put my own VHDL microcomputer definition in a commented gist, which should help explain what’s going on a little better. This build is for a Z80 running BASIC and 4K of internal 8bit RAM. It has a UART (a 6850 compatible one) and an IO device called “aaron” which I’ll explain later.

In fact, my whole project file is available for download.

Quartus is as powerful as it is kind-of ugly:

When I imported Grant’s project Quartus asked me to upgrade the IP, which I’ve done. I regenerated the the RAM and ROM using the wizard interface, as they are built using “off the shelf” Altera IP blocks.

You just specify how much RAM you want to use, how many ports it should have (you can have dual port RAM, useful for framebuffers) and how wide the data bus should be.

For the ROM you can see I picked 8K of 8bit words, and it’s going to have 12 address signals and 8 data signals:

I also had to define which pins on the chip I wanted to use for each of the external signals – not every pin can be used for every function but it’s surprisingly flexible:

Congratulations! This should be all you need to synthesise your design. If you were on Windows, you could even use the built in programmer software to upload it, but for some reason, that didn’t work for me.

Tune in next time to see how I got JTAG programming working, and for the exciting “Hello, World”.